Deep Learning & FPGA (with NTU NetDB)

Lab Topic Learning Objectives Slides Code Video Updated
Textbooks and References GitHub
1-1 Verilog & FPGA
(Dr. Chia-Chen Yen)
  • PYNQ-Z2 Hardware/FPGA Architectures
  • Block Design
  • PYNQ Overlay
 ppt Code 2020/8/17
1-2 Verilog & FPGA
(Dr. Chia-Chen Yen)
  • Verilog Basics
  • Design full adder using Vivado
1-3 Verilog & FPGA
(Dr. Chia-Chen Yen)
  • Block Design
  • PYNQ Overlay
1-4 CFGLUT5 (1)
(Dr. Chia-Chen Yen)
  • Look-up Table (LUT)
  • 5-input Dynamically Reconfigurable (LUT)
1-5 CFGLUT5 (2)
(Dr. Chia-Chen Yen)
  • Look-up Table (LUT)
  • 5-input Dynamically Reconfigurable (LUT)