Xilinx FPGA & Deep Learning

Taipei Tech FPGA

Lab Topic Learning Objectives Slides Code Video Updated
Textbooks and References GitHub
0 PYNQ-Z2 Setup
  • Create Boot Image
  • Setup Board
  • Connect to Host Computer
PYNQ Setup 2021/3/4
1 Xilinx PYNQ-Z2
(Ack.: 一元素科技)
  • FPGA Architectures
  • PYNQ-Z2 Hardware
  • Block Design
  • PYNQ Overlay
1_PYNQ_Intro
Xilinx_PYNQ
2021/2/24
2 Vivado IDE
  • Xilinx Vivado HLS
  • FPGA Design Process
  • Design Optimization
2_vivado 2021/3/4
3 FIR Filter
  • Xilinx Vivado HLS
  • Finite Impulse Filter (FIR)
  • Loop Unrolling
  • Loop Pipelining
3_FIR 2021/3/11
4 AXI Protocol
  • What is AXI?
  • AXI Interconnection
  • AXI Stream Interface
4_AXI 2021/3/11
5 Cordic 5_CORDIC 2021/4/1
6 Cordic DPU on PYNQ-Z2 2021/4/15