Xilinx FPGA & Deep Learning

Taipei Tech FPGA       Playlist

Lab Topic Learning Objectives Slides Code Video
Textbooks and References GitHub
0 PYNQ-Z2 Setup
  • Create Boot Image
  • Setup Board
  • Connect to Host Computer
PYNQ Setup
1 Xilinx PYNQ-Z2
(Ack.: 一元素科技)
  • FPGA Architectures
  • PYNQ-Z2 Hardware
  • Block Design
  • PYNQ Overlay
1_PYNQ_Intro
Xilinx_PYNQ
2 Vivado IDE
  • Xilinx Vivado HLS
  • FPGA Design Process
  • Design Optimization
2_vivado
3 FIR Filter
  • Xilinx Vivado HLS
  • Finite Impulse Filter (FIR)
  • Loop Unrolling
  • Loop Pipelining
3_FIR
4 AXI Protocol
  • What is AXI?
  • AXI Interconnection
  • AXI Stream Interface
4_AXI
5 DPU on PYNQ-Z2 (1) DPU on PYNQ-Z2.pdf Lab Video
6 DPU on PYNQ-Z2 (2) Peta Linux
  • DPU project Architecture
  • What is petalinux?
  • Build pynqz2_dpu boot binary file
petalinux.pdf Lab Video
7 DPU on PYNQ-Z2 (3): DNNDK
  • Deep Neural Network Development Kit (DNNDK)
DNNDK.pdf bin_image
8 Cordic CORDIC
9 DFT and FFT
  • Discrete Consine Transform (DCT)
  • Fast Fourier Transform (FFT)
DFT_FFT.pdf
10 Sparse Matrix Multiplication
sparse_matrix_mult.pdf
11 Pre-sum and Histogram
  • Prefix Sum
  • Histogram
Prefix-sum_n_Histogram.pdf
12 Matrix Multiplication (1)
matrix_mult1.pdf
13 Matrix Multiplication (2) and Final Review
matrix_mult2.pdf