Deep Learning on FPGA

Xilinx FPGA & Deep Learning

Lab	Topic	Learning Objectives	Slides	Code
	Textbooks and References	KRG @ UC San Diego, “Parallel Programming for FPGAs”, 2018		GitHub
0	PYNQ-Z2 Setup	Create Boot Image Setup Board Connect to Host Computer	PYNQ Setup
1	Xilinx PYNQ-Z2 (Ack.: 一元素科技)	FPGA Architectures PYNQ-Z2 Hardware Block Design PYNQ Overlay	1_PYNQ_Intro Xilinx_PYNQ
2	Vivado IDE	Xilinx Vivado HLS FPGA Design Process Design Optimization	2_vivado
3	FIR Filter	Xilinx Vivado HLS Finite Impulse Filter (FIR) Loop Unrolling Loop Pipelining	3_FIR
4	AXI Protocol	What is AXI? AXI Interconnection AXI Stream Interface	4_AXI
5	Matrix Multiplication (1)		matrix_mult1.pdf
6	Matrix Multiplication (2)		matrix_mult2.pdf
7	DFT and FFT	Discrete Consine Transform (DCT) Fast Fourier Transform (FFT)	DFT_FFT.pdf
8	Sorting
9	Systolic Array
10	DPU on PYNQ-Z2 (1)		DPU on PYNQ-Z2.pdf	Lab Video
11	DPU on PYNQ-Z2 (2) Peta Linux	DPU project Architecture What is petalinux? Build pynqz2_dpu boot binary file	petalinux.pdf	Lab Video
12	DPU on PYNQ-Z2 (3): DNNDK	Deep Neural Network Development Kit (DNNDK)	DNNDK.pdf	bin_image
13	Cordic		CORDIC
14	Sparse Matrix Multiplication		sparse_matrix_mult.pdf
15	Pre-sum and Histogram	Prefix Sum Histogram	Prefix-sum_n_Histogram.pdf